This patent application claims the priority of Korean Patent Application 2003-17598 filed on Mar. 20, 2003 in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
1. Technical Field
The present disclosure relates to a semiconductor memory device, more particularly to an internal voltage generating circuit of a semiconductor memory device.
2. Discussion of the Related Art
An internal voltage generating circuit of a conventional semiconductor memory device includes an internal voltage generating circuit for a memory cell array and an internal voltage generating circuit for a peripheral circuit of the memory cell array.
The internal voltage generating circuit for the memory cell array supplies an internal voltage to a positive channel metal oxide semiconductor (PMOS) bit line sense amplifier which senses a voltage of a bit line and amplifies it to an internal voltage level.
The internal voltage generating circuit for the memory cell array of the conventional semiconductor memory device includes an overdriving transistor in order to prevent a drop of an internal voltage generated when a bit line sensing operation is performed. The internal voltage level rises before the bit line sensing operation is performed and, thus a level drop of an internal voltage is prevented when the bit line sensing operation is performed. Hence, the bit line can be rapidly amplified to an internal voltage level, so that read and write speeds are not delayed.
FIG. 1 is a circuit diagram illustrating a conventional internal voltage generating circuit. The internal voltage generating circuit 10 includes a comparator 11, a negative channel metal oxide semiconductor (NMOS) transistor N1, and a PMOS transistor P1.
In FIG. 1, the NMOS transistor N1 is an overdriving control transistor for controlling overdriving of the PMOS transistor P1, and the PMOS transistor P1 is a driver for driving an internal voltage VCCA. “VREFA” represents a reference voltage for an internal voltage VCCA, “VEXT” represents an external power voltage which is applied from an external portion of a semiconductor memory device, “PACT” represents an active signal and a pulse signal which has a predetermined pulse width generated before an active command is applied to a semiconductor memory device and the bit line sensing operation is performed.
In operation, when an active signal PACT having a “low” level is applied to turn off the NMOS transistor N1 of the internal voltage generating circuit 10 of FIG. 1, the PMOS transistor P1 performs a normal driving operation. In contrast, when an active signal PACT having a “high” level is applied to turn on the NMOS transistor N1, the PMOS transistor P1 performs an overdriving operation.
When the internal voltage VCCA is lower than the reference voltage VREFA during a normal driving operation, the comparator 11 compares the internal voltage VCCA to the reference voltage VREFA and then lowers a voltage of a node A. As a result, a driving ability of the PMOS transistor P1 is increased and then the internal voltage VCCA increases.
On the other hand, when the internal voltage VCCA is higher than the reference voltage VREFA during a normal driving operation, the comparator 11 compares the internal voltage VCCA to the reference voltage VREFA and then increases a voltage of a node A. As a result, a driving ability of the PMOS transistor is decreased and then the internal voltage VCCA decreases.
The internal voltage generating circuit repeatedly performs the operations described above during a normal driving operation to maintain the internal voltage VCCA at the same level as the reference voltage VREFA.
During an overdriving operation, the NMOS transistor N1 is turned on to lower a voltage level of a node A less than during a normal driving operation. As a result, a driving ability of the PMOS transistor P1 is improved when compared with a normal driving operation to overdrive a level of the internal voltage VCCA to a level higher than the reference voltage VREFA.
However, when an external power voltage VEXT increases, a voltage difference between a gate and a source of the PMOS transistor P1 becomes greater, so that a driving ability of the PMOS transistor P1 is more improved than needed, whereby a level of the internal voltage VCCA is overshot. That is, the internal voltage VCCA is much higher than a desired voltage (hereinafter, target voltage) for overdriving.
When the internal voltage VCCA is overshot or higher than a target voltage, a bit line voltage level also becomes higher. As a result, a sensing time is delayed during write and read operations, leading to a delay in data write and read speed.
FIG. 2 is a graph illustrating a variation of an internal voltage VCCA with respect to an active signal PACT in the conventional internal voltage generating circuit 10. A solid line represents performance of an overdriving operation, and a dotted line represents an occurrence of overshooting, wherein the internal voltage VCCA is higher than a target voltage.
As shown in FIG. 2, in the case that an active signal PACT having a predetermined pulse width is generated, when an external voltage VEXT of a low level is applied, an internal voltage VCCA which maintains a level of a reference voltage VREF is overdriven by an amount equal to a voltage Δ, and reaches a target voltage VREF+Δ, as shown by the solid line. However, as shown by the dotted line, when an external voltage VEXT of a high level is applied, an internal voltage VCCA increases to a voltage level beyond a target voltage VREFA+Δ. Hence, during a bit line sensing operation, a level of an internal voltage VCCA does not decrease to reach a level of the reference voltage VREFA and instead maintains a voltage level higher than VREFA, that is, VREFA+δ.
As described above, in the conventional internal voltage generating circuit, when a level of an external voltage VEXT is heightened, an overshooting occurs, thereby increasing the internal voltage VCCA to a level higher than a target voltage during an overdriving operation, so that the internal voltage VCCA does not thereafter decrease to a reference voltage level. As a result, a sensing time is increased during a bit line sensing operation, leading to a delay in data write and read speed.